1. Field of the Invention
The present invention relates to a refresh method of a semiconductor memory device, and particularly to a refresh method of reusing electric charges in which the charges that are charged/discharged to a bit line and its complementary bit line via common source lines when performing a refresh operation in one memory array are also used for performing an initial refresh operation of another memory array, thereby reducing refresh current requirements.
2. Description of the Conventional Art
Referring to FIG. 1, there is shown a construction of a conventional memory array whereby, the conventional 4-MBit memory array includes a memory unit 10 for writing and reading data to/from memory cells connected to a plurality of word lines WL1 to WLn and a plurality of bit line pairs BL1, BLB1, . . . BLn, BLBn; a sense amplification unit 20 respectively connected to bit lines pairs BL1, BLB1, . . . BLn, BLBn of the memory unit 10 for performing a sensing operation of data; and a power supply unit 30 for supplying electric power to the sense amplification unit 20.
The sense amplification unit 20 includes a plurality of CMOS sense amplifiers S/A1 to S/An. The sense amplifier S/A1 of the sense amplification unit 20 includes PMOS transistors 11 and 12 each having a source connected to a common node N5, a drain connected to the bit line BL1 and its complementary bit line BLB1 respectively, and a gate to which the bit line BL1 and its complementary bit line BLB1 are crosswise connected; and NMOS transistors 13 and 14 each having a source connected to a common node N6, a drain connected to the bit line BL1 and its complementary bit line BLB1 respectively, and a gate to which the bit line BL1 and its complementary bit line BLB1 are crosswise connected. The structure of the sense amplifiers S/A2 to S/An is similar to that of the sense amplifier S/A1.
The power supply unit 30 includes a PMOS transistor 15 having a source to which a supply voltage Vcc is applied, a gate to which a row address strobe signal RAS outputted from a RAS signal generator is inputted, and a drain to which the common node N5 of the plurality of sense amplifiers S/A1 to S/An is connected; and an NMOS transistor 16 having a source to which a ground voltage Vss is applied, a gate to which a signal/RAS outputted from the RAS signal generator is inputted, and a drain to which the common node N6 of the sense amplifiers S/A1 to S/An is connected.
In the case of a 16-Mbit semiconductor chip, four (4) 4-MBit memory arrays having the above-described structure are included.
A "CAS (column address strobe) Before RAS" refresh method of the 4-MBit memory array in the conventional semiconductor chip is explained referring to FIGS. 1 and 2.
First, when a word line WL1 is selected by a refresh counter, data "0" is outputted to a bit line BLB1 from a memory cell connected to the selected word line WL1 and the bit line BLB1 . The outputted data "0" is inputted to each gate of the NMOS transistor 13 and the PMOS transistor 12 of the sense amplifier S/A1 via the nodes N1 and N2, thereby causing the NMOS transistor 13 to be turned off and the PMOS transistor 12 to be turned on.
When the signals RAS and/RAS of FIG. 2B are respectively applied to the gates of the PMOS transistor 15 and the NMOS transistor 16 of the power supply unit 30, the PMOS transistor 15 and the NMOS transistor 16 are turned on, and thereby the supply voltage Vcc and the ground voltage Vss are respectively inputted to the common nodes N5 and N6 of the sense amplifier S/A1 via common source lines CSL1 and CSL2.
Afterwards, the supply voltage Vcc inputted to the common node N5 is applied to the bit line BL1 via the PMOS transistor 12 which is turned on, and the bit line BL1 being maintained at one-half the supply voltage 1/2Vcc is charged to the supply voltage Vcc level. The charged electric charges are inputted to the gates of the PMOS transistor 11 and the NMOS transistor 14 of the sense amplifier S/A1 via the nodes N3 and N4.
Accordingly, the PMOS transistor 11 is turned off and the PMOS transistor 14 is turned on. The electric charge of the bit line BLB1 being maintained at one-half the supply voltage Vcc, i.e., to 1/2Vcc are discharged via the common source line CSL2 and maintained at the ground voltage Vss level. Thereafter, when a word line WL1 is disabled, the bit line BL1 and its complementary bit line BLB1 become charged at the level of one-half the supply voltage Vcc, namely, to 1/2Vcc.
Further, the refresh processes of the sense amplifiers S/A2 to S/An are similar to those of the sense amplifier S/A1.
The refresh operation of each 4-MBit memory array is explained as follows. The word line is selected by the refresh counter, and after the sense amplifiers are driven by using the data stored in the memory cells connected to the selected word line, the electric charges are charged/discharged to the bit line BL and its complementary bit line BLB by the voltage of the power supply unit.
However, when the "CAS Before RAS" refresh operation of the 4-MBit memory array is performed, a peak current, i.e., refresh current flows at the time the electric charges are charged/discharged to the bit line BL and its complementary bit line BLB, as shown in FIG. 2C.
Accordingly, in the case of a 16-Mbit semiconductor chip where four (4) 4-Mbit memory arrays respectively perform a refresh operation, the refresh current is increased and there are difficulties in decreasing the noise margin and meeting the memory characteristic requirements when designing semiconductor chips. Particularly, for notebook computers or personal data apparatuses, there is a problem in that the life of dry cells or batteries becomes short since the battery backup current is increased.